Semiconductor devices are manufactured by forming active regions in a semiconductor substrate, depositing various insulating, conductive, and semiconductive layers over the substrate, and patterning them in sequential steps. After a semiconductor device such as a CMOS device has been created, electrical access to the device must be provided. This electrical contact may, for reasons of device performance, be a low-resistivity contact. Silicide layers may provide low resistivity contacts. Salicidation is the term used for self-aligned silicide. The process of salicidation is well known in the art. Salicided layers can be formed comprising titanium silicide (TiSi2), cobalt silicide (CoSix), and nickel silicide (NiSix), for example.
The method of self-aligned silicide (salicide) formation, which self-registers with the contacts at the top of the polysilicon gate, the source, and the drain, solves a problem of critical dimension tolerance. Salicides are typical in high-density CMOS devices. There are, however, problems associated with prior art methods of salicide formation. One main problem is that the salicidation process of converting a metal to its silicide is achieved by the consumption of silicon underlying the metal, and this means the consumption of substrate silicon in the regions of the source and drain. The source/drain junctions may be shallow in sub-half-micron devices and the salicidation process may cause the junctions to become thin. Further, a salicidation reaction may consume substrate silicon unevenly, leading to ragged source/drain junctions or the creation of spikes that may penetrate through the junctions near the edges of the source/drain areas.
Another issue in device salicide processing is the use of silicide films for stress enhanced device performance. Among other layers, the silicide films may add beneficial stresses to the NMOS and PMOS transistors. An added complication is that the NMOS and PMOS transistors may benefit from different stresses, for example, an NMOS device may benefit from a tensile stress lateral across the channel region, while a lateral stress across the PMOS channel is detrimental. Producing low resistance, advantageously stressed silicide films has been a challenge.